- ...fault)
- The consistency fault mechanism is used to
implement a consistency protocol on a cache-line basis for distributed
shared memory, providing a finer-grain consistency unit than pages.
A consistency trap also occurs if a reference is made to a memory
module that has failed.
- ...delivery
-
The ParaDiGM hardware [7] provides
automatic signal-on-write
to memory in message mode,
delivering an address-valued signal to each processor
managing a signal thread for the page
when a thread writes a cache line in message mode.
It also provides message-oriented consistency on pages in message mode,
allowing a processor (presumably the sender) to write a cache line
without requiring any ``ownership'' of the line.
When the write completes, the cache controller updates
other cached copies of the line as necessary.
This specialized consistency minimizes the cache consistency overhead
for memory used purely for messaging.
The design also calls for hardware delivery of the signal using
a per-processor reverse-TLB that maps physical addresses
to the corresponding virtual address and signal handler function pairs
so there is no software intervention on a reverse-TLB hit.
At present, our hardware supports automatic signal generation but not
delivery, so the missing portion is emulated in a tightly
coded part of the Cache Kernel. Conventional hardware requires
software support for generating the signal as well as signal
delivery, but this software is a minor extension of the current
Cache Kernel mapping mechanisms.
- ...cache
- Our hardware has 32-byte cache
line size, 8 megabytes of cache, and a page size of 4k (128
lines).